In the formation of semiconductor devices, it is necessary to provide both desired electrical contact between certain regions of the devices formed and also to prevent contact between various other regions of the devices formed on the substrate. One technique for accomplishing this has been by using photoresist and masking techniques whereby those areas to be exposed for electrical contact are patterned in the photoresist and then by developing the patterned photoresist, to thereby expose the desired underlying regions. This technique normally requires several successive masks to perform the entire process, and in its performance each succeeding mask must be precisely aligned. However, as the technology advances, allowing for formation of smaller and smaller devices, it is increasingly difficult to maintain precise overlay tolerance, with the result that even small misalignments of the masks will result in the exposure of small portions of regions that are intended to remain covered. Hence, electrical connections, e.g. by an overlay deposition of a electrically conductive material such as a metal, will connect not only the desired locations, but also those exposed portions of the undesired locations.
Accordingly, in order to achieve decreased cell size along with the number of alignment levels in semiconductor devices, self-aligned contact etching has been widely employed. For instance, many etch applications require using a self-aligned feature to minimize mask levels and cell size as illustrated in FIG. 1. For instance, as illustrated in FIG. 1, the gate 10 is protected or capped by a dielectric layer 11 which is typically a silicon nitride. Above layer 11 is a second, chemically different dielectric material 12 such as a silicon oxide. During the etching process to provide the subsequent contact 13 to the underlying semiconductor substrate (not shown) the corner of the dielectric capping is exposed to the etching process. However, in such a process, selectivity to the corner of the underlying material is essential.
In dry etch processes such as high density plasma, achieving this selectivity is often quite difficult due to high ion flux. This is especially pronounced in high aspect ratio features as schematically shown in FIG. 2. Plasma electrons, being highly mobile, are primarily thermal in nature and therefore tend to migrate to the surface of an etched feature. In contrast, positive plasma ions are driven primarily drift through the plasma sheath, and are highly anisotropic. Since the time integrated current to the semiconductor substrate or wafer over one RF cycle must be zero, a net surface charge on dielectric materials can be induced. The shallow entrance of the feature charges negatively as most electrons are captured there, and the deeper features charge positive since positive ions are nearly as likely to reach the bottom of the feature as they are the top. This top to bottom negative potential results in a curvature of positive ions towards the corners of the etched front, and causes the difficulty in achieving selectivity of the self-aligned feature corner.
As device dimensions are reduced, the aspect ratio of the self-aligned contact etch becomes more severe. This further worsens the degree of charging observed, and consequent further corner erosion. New approaches are therefore required to provide self-alignment to underlying features.
Presently, the process for forming self-aligned contact includes a relatively thick nitride cap and spacer to compensate for the loss of selectivity on the feature corner. However, the corner selectivity achieved with the etching process, combined with the thick nitride is marginal for self-aligned contact technology. Moreover, currently the etching processes must observe a relatively narrow process window, due to the excessive polymerization level necessary to achieve corner selectivity.